kla

broadband plasma (BBP) division | input data adapter (IDA) team
managers: wes nakamura, rish patel
project mentors: frank chao, johnny trinh

tools: systemverilog, questa, vivado, python
company website | division website

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intro

KLA (formerly KLA-Tencor) is a leading provider of process control and yield management solutions for the semiconductor industry. Their high-precision tools detect defects and manage manufacturing variability, ensuring optimal yield and performance in microchip fabrication. KLA’s solutions broadly fall under three categories:

• Inspection: High-powered optical and electron-beam systems that scan silicon wafers and photomasks for flaws.
• Metrology: Tools that measure the physical dimensions of chip features, such as layer thickness or pattern alignment, to ensure they match the architectural design.
• Data Analytics: Software analyzes the data to identify where manufacturing issues occur.

Examples of KLA inpsection tools.

I worked within KLA’s Broadband Plasma (BBP) division, which develops “brightfield” optical inspection systems. These advanced tools scan wafers using light wavelengths ranging from visible to deep ultraviolet (DUV), balancing high inspection throughput with sub-resolution image fidelity. In contrast to electron-beam systems (which offer higher resolution but much slower throughput), brightfield tools serve as the high-speed workhorse for defect detection in high-volume manufacturing.

You can read more about KLA’s BBP tools in this article!

my work

I designed and implemented a hardware-accelerated compression pipeline to manage the massive data throughput generated by KLA inspection tools. At production speeds (processing hundreds of wafers per hour at hundreds of gigabytes per wafer), data transfer quickly becomes a bottleneck. To address this, we implemented the JPEG-LS (lossless JPEG) algorithm on a reconfigurable FPGA card to enable real-time, line-speed compression.

Pixels A --> D used to predict next pixel X in JPEG-LS.

The architecture utilizes predictive coding: a spatial predictor estimates the value of incoming pixels based on neighboring context, encoding only the difference (residual) between the actual and predicted values. By incorporating a “run-length” mode for uniform intensity regions, the design is optimized for the high-contrast geometries characteristic of photomask and silicon wafer layouts, maximizing compression ratios while ensuring bit-perfect data integrity.

Alveo U50 FPGA accelerator card I targeted for this design.

To meet throughput requirements, I overhauled the initial decompression design to integrate a high-performance JPEG-LS engine. I architected a system-level control framework to manage parallel data distribution and frame reconstruction across multiple decompression cores. Using AMD Vivado IP Integrator for hardware synthesis and Siemens Questa for RTL simulation, I resolved critical frame-stitching and synchronization boundaries at the core interfaces. I optimized resource utilization on the target Alveo U50 FPGA and validated the end-to-end pipeline’s performance using KLA’s hardware-in-the-loop benchmarks, successfully transitioning a standalone IP block into a production-ready accelerator.

photos!

Introduction/status cards I made for my "box" (cubicle)

Intern tour of the clean room; me in a bunny suit!

Making electronics kits for local high school students with the KLA foundation

Group photo of all the Milpitas HQ interns

acknowledgements

IDA team photo, August 2025

A massive thank you to the IMC/IDA team for welcoming me with open arms. From competitive pickleball and boba runs to sharing our mechanical keyboard builds and putting fences together, I had an absolute blast.

To my managers, Rish Patel and Wes Nakamura: thank you for the endless mentorship and for trusting me with such a critical project. And to Coen Warmenhoven and Natalie Cooper: thank you for opening the door to this unforgettable summer.

Thanks also to Johhny Trinh for inspiring me to make this website in Jekyll :)