18-341: logic design and verification

tools: systemverilog, vcs

💡 practical application

Universal Serial Bus (USB) is the universal standard connecting keyboards, mice, flash drives, and chargers to computers. Connecting a flash drive requires a complex series of low-level electrical signals, handshakes, error checks, and data translations. This project designed the underlying silicon hardware engine (a Serial Interface Engine) that manages the electrical communication and protocols necessary to read data from external USB storage drives securely and reliably.

intro

This project designed a synthesizable USB 2.0 Host Serial Interface Engine (SIE) in SystemVerilog, verified in simulation using VCS. Working entirely at RTL, the host implements a multi-threaded architecture that interfaces with an encrypted thumb drive model. The engine manages physical-layer signaling, NRZI clock extraction, transaction error recovery, and memory paging.

USB Host Block Diagram
System block diagram of the USB Host.

bit-level engine

The physical-layer engine translates differential bus signals (DP and DM) into clean data packets. On the transmit path, the bitstream passes through:

  1. CRC Generators: Computes 5-bit CRCs for token packets and 16-bit CRCs for data packets.
  2. Bit Stuffer: Inserts a zero-bit after detecting six consecutive ones to prevent receiver clock drift.
  3. NRZI Encoder: Toggles output states on zeros and maintains states on ones, using tri-state bus drivers for single-ended zero (SE0) sequences.

The receive path mirrors this flow through an NRZI decoder, bit unstuffer, and parallel CRC checker.

Stream Encode CRC Datapath Stream Encode CRC FSM
Stream encoder and CRC datapath/FSM layout.

Bit Stuffer Diagram
Bit stuffer module state machine and logic.

NRZI Datapath and FSM
NRZI encoder/decoder datapath and FSM state transition diagrams.

protocol handler

Operating above the serial bitstream, the protocol handler converts high-level read/write commands into standard USB packet sequences (OUT, IN, DATA0, ACK, NAK).

Custom SV Types
Custom SystemVerilog packet and transaction struct definitions.

To handle physical bus noise and missing responses, the protocol handler uses a robust error-recovery FSM:

  • Timeout Detection: Uses an 8-bit timer to detect device silence, declaring a timeout if the device fails to respond within 255 clock cycles.
  • NAK & Retry Arbitration: If a packet is corrupted (violating CRC residues) or times out, the host returns a NAK and retries the transaction up to 7 times before aborting.

Protocol Handler IN FSM Protocol Handler OUT FSM
Protocol handler state machines for IN (left) and OUT (right) transactions.

verification & simulation

The host was verified in simulation using VCS against edge-case test suites:

  • Edge Data Patterns: Maximum bit-stuffing transitions and boundary-value CRC calculations.
  • Stress Cycles: 100 random sequential reads and writes to verify address paging logic and FSM stability.
  • Fault Injection: Synthetic packet corruptions, timeouts, and abort scenarios to confirm error recovery up to the 7-retry limit.

Thank you to the 18-341 course staff for simulation testbenches and checkoff support.