18-341: logic design and verification

tools: systemverilog, vcs

💡 practical application

Modern microprocessors contain dozens of individual processor cores and memory blocks that must constantly exchange data. Instead of cluttering the chip with thousands of individual direct wires, a Network-on-Chip acts like an internal postal service or internet router directly on silicon—packaging data into small packets and routing them to their destinations efficiently without causing digital traffic jams.

intro

A hardware-based Network-on-Chip (NoC) prototype modeled in SystemVerilog and verified through simulation using VCS. Operating entirely at the register-transfer level (RTL), the system implements a complete packet-switched routing network with distributed nodes and multi-port routers, transferring packets between multiple concurrent hardware components.

network architecture

To enable communication between multiple independent components, we designed a topology consisting of two central routers and six terminal nodes. Packets are injected into the nodes from testbench components as 32-bit words containing source, destination, and payload data.

Each router is composed of four RouterCorner modules. When a corner receives a packet, it checks the destination address via a PortChecker, routing it to the appropriate output corner of the router. If a packet’s destination node resides on a different router, it is forwarded across a dedicated bridge link between the two routers.

Router Ports Connections
Router port connections (Router 0 example).

packet serialization

To transmit data efficiently over narrow physical channels without requiring wide, expensive busses, the nodes serialize 32-bit packets into 8-bit bytes before sending them to the router. The communication uses a strict handshake protocol (free_outbound/put_outbound) to prevent buffer overflows.

Node Internal Diagram
Node internal architecture showing serialization and deserialization blocks.

We designed dedicated inbound and outbound datapaths for each node direction to process the serialization and deserialization concurrently:

Inbound Datapath Inbound FSM
Inbound datapath and FSM state diagrams.

Outbound Datapath Outbound FSM
Outbound datapath and FSM state diagrams.

priority arbitration

A primary challenge in packet-switched routers is handling port contention when multiple input ports simultaneously request to route packets to the same output port.

To resolve conflicts and ensure transaction fairness, we designed a Least-Recently Used (LRU) pointer-based priority arbiter (Handler). This arbiter tracks which ports have recently transmitted and dynamically shifts priority ordering. Under high-load stress testing, this round-robin mechanism successfully prevented packet starvation, routing concurrent requests with a balanced distribution to maintain strict fairness.

Arbiter Datapath and FSM
LRU round-robin priority arbiter datapath and FSM.

Thank you to the course staff in 18-341 for the simulation testbenches and checkoff support!