18-341: logic design and verification

tools: systemverilog, vcs

💡 practical application

Modern microprocessors contain dozens of individual processor cores and memory blocks that must constantly exchange data. Instead of cluttering the chip with thousands of individual direct wires, a Network-on-Chip acts like an internal postal service or internet router directly on silicon—packaging data into small packets and routing them to their destinations efficiently without causing digital traffic jams.

intro

This project built a hardware-based Network-on-Chip (NoC) prototype in SystemVerilog, verified through simulation using VCS. Operating entirely at RTL, the system implements a packet-switched routing network with distributed nodes and multi-port routers, transferring packets between multiple concurrent hardware components.

network architecture

To enable communication between independent components, the topology uses two central routers and six terminal nodes. Packets inject into nodes as 32-bit words containing source, destination, and payload data.

Each router consists of four RouterCorner modules. When a corner receives a packet, it checks the destination address via a PortChecker, routing it to the appropriate output corner. If a packet’s destination node resides on the opposite router, it forwards across a dedicated bridge link between the two routers.

Router Ports Connections
Router port connections (Router 0 example).

packet serialization

To transmit data efficiently over narrow channels without requiring wide buses, nodes serialize 32-bit packets into 8-bit bytes before sending them to the router. Communication uses a strict handshake protocol (free_outbound/put_outbound) to prevent buffer overflows.

Node Internal Diagram
Node internal architecture showing serialization and deserialization blocks.

Dedicated inbound and outbound datapaths for each node direction process serialization and deserialization concurrently:

Inbound Datapath Inbound FSM
Inbound datapath and FSM state diagrams.

Outbound Datapath Outbound FSM
Outbound datapath and FSM state diagrams.

priority arbitration

Port contention occurs when multiple input ports simultaneously request to route packets to the same output port.

To resolve conflicts and guarantee transaction fairness, we designed a Least-Recently Used (LRU) pointer-based priority arbiter (Handler). This arbiter tracks which ports have recently transmitted and dynamically shifts priority ordering. Under high-load stress testing, this round-robin mechanism prevented packet starvation, routing concurrent requests with a balanced distribution to maintain strict fairness.

Arbiter Datapath and FSM
LRU round-robin priority arbiter datapath and FSM.

Thank you to the 18-341 course staff for simulation testbenches and checkoff support.