matmul

18-341: logic design and verification

tools: systemverilog, vcs, quartus

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💡 practical application

Matrix multiplication is the fundamental mathematical operation behind Artificial Intelligence (like ChatGPT), graphics rendering, and computer vision. Calculating massive grids of numbers in software requires billions of sequential steps. This project built a dedicated silicon hardware engine (a pipelined systolic array) that solves giant matrix equations in parallel, dramatically speeding up AI calculations while using less energy.

intro

This project built a hardware-accelerated matrix multiplier in SystemVerilog, simulated with VCS, synthesized using Altera Quartus Prime, and deployed on a DE0-CV Development Board (Cyclone V FPGA). Operating entirely at RTL, the engine computes $Y = A \times B + C$ using hardware pipelines, maximizing parallel throughput under a 70 MHz timing constraint.

matrix multiply

The system solves $Y = A \times B + C$, where $A$ is a $128 \times 128$ matrix (8-bit values), $B$ is a $128 \times 1$ column vector (8-bit values), and $C$ is a $128 \times 1$ column vector (16-bit values), outputting the sum of all elements in the 24-bit $Y$ vector.

Instead of computing $Y$ element-by-element and storing intermediate vectors (which consumes memory and clock cycles), we algebraically simplified the summation: $$Result = \sum_{i=0}^{127} Y_i = \sum_{i=0}^{127} \left( \sum_{j=0}^{127} A_{ij} B_j + C_i \right)$$

This mathematical reformulation separates the computation into two parallel pathways: accumulating the matrix product $A \times B$ while independently summing vector $C$.

RAM/ROM layout mapping matrix storage across Cyclone V block RAMs.

parallel architecture & pipelining

To achieve high cycle efficiency, the design uses 272 M10K block RAMs and 32 embedded multipliers.

The architecture instantiates 16 parallel MiniMultiplier modules. Dual-port M10K RAMs allow each module to read two adjacent values ($A$ horizontally and $B$ vertically) per clock cycle. Two combinational multipliers ($A_1 \times B_1$ and $A_2 \times B_2$) compute products, which latch into an accumulator register.

Parallel execution pathway for A × B matrix multiplication across 16 mini-multiplier lanes.

To aggregate outputs from 16 parallel lanes without long combinational paths that violate the 70 MHz timing limit, we built a 4-tier pipelined reduction tree. Each tier uses AdderRegister modules to sum intermediate pairs. The final tier adds the sum to a running total register over cycles 9 to 520, completing $A \times B$ accumulation in 521 cycles.

Sequential accumulator pathway used to sum vector C elements.

Vector $C$’s 128 elements sum sequentially in 128 cycles, finishing before the $A \times B$ pathway completes. The final result combines both sums.

controls & debugging

SW[0] toggles 7-segment hex display output (HEX5 through HEX0): setting the switch to 1'b0 displays the 24-bit accumulated sum, while 1'b1 displays total clock cycles. Internal status signals (done, active) route to board LEDs (LEDR) for real-time hardware monitoring.

Thank you to the 18-341 course staff for lab resources and compilation support.