pong
pong game and VGA engine
november 2023
pittsburgh, pa
18-240: structure and design of digital systems
teammates: william chen
tools: systemverilog, vcs, quartus
Modern video games run using software code, computer processors, and operating systems. In contrast, this project recreated the classic game Pong entirely in custom hardware circuits on a programmable chip. Every pixel, paddle movement, score counter, and display signal is calculated instantly by dedicated physical logic gates, demonstrating how computer graphics can render in real time without needing a central processor or operating system.
intro
A hardware-based VGA graphics engine and fully functional Pong video game modeled in SystemVerilog, simulated and verified using VCS, synthesized with Altera Quartus Prime, and deployed onto a physical DE2-115 Development Board (Cyclone IV FPGA). Operating entirely at the register-transfer level (RTL), the system runs directly on clock division and hardware timers without soft-core processors or software instructions.
VGA engine
We began by designing a custom VGA graphics engine to drive a standard 640x480 resolution at 60Hz. Because the FPGA board operates on a fixed 50 MHz clock, we used clock division and comparison math in SystemVerilog to keep track of the monitor’s “scan beam” position.
By tracking horizontal and vertical counters, the hardware precisely calculated when the scan was in the active display region, or when it entered the blanking intervals (front porch, sync pulse, and back porch).
The 8-color bar test pattern output on a VGA monitor to confirm timing stability.
To verify our timing logic on a physical monitor before layering any complex game logic, we created a static test pattern generator. This generator divided the screen into vertical color bars on the top half and a solid black region on the bottom half, confirming that our color channels, active blanking, and sync pulses were completely aligned and stable.
pong game
Once we had a stable display foundation, we built the Pong game mechanics directly on top of it. Our graphics engine dynamically checked whether the current scan coordinates fell within the boundaries of our paddle and ball registers, rendering them on-the-fly against a dark blue background.
Designing game physics in pure hardware introduced a classic timing challenge: if the ball and paddles updated their coordinates on every clock cycle of our 50 MHz master clock, the game would run too fast to be visible.
To solve this, we implemented a frame-rate synchronization circuit. Using a D-flip-flop division loop, we asserted a frame_finished trigger exactly once per video frame (specifically when the “scan beam” reached the bottom-right corner of the screen). This restricted the physics logic to update at a clean 60Hz. During each update, the datapath checked for overlapping bounding boxes between the ball, paddles, and screen edges, reversing velocity vectors ($dx, dy$) upon collision.
controls & debugging
For user inputs, players controlled the left and right paddles using toggle switches on the DE2-115 board to select directions and enable movement.
FPGA Pong game in action on the monitor.
We routed the scoring counters through a decimal decoder to display scores on the board’s 7-segment displays (HEX7 through HEX4). Additionally, to make debugging on physical hardware much easier, we mapped our FSM’s active state codes directly to HEX0. This gave us a real-time visual indicator of the game’s state transitions, allowing us to quickly diagnose FSM errors.
Thank you to the course staff in 18-240 for supplying the DE2-115 kits and lab resources!