pong

18-240: structure and design of digital systems
teammates: william chen

tools: systemverilog, vcs, quartus

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💡 practical application

Modern video games run using software code, computer processors, and operating systems. In contrast, this project recreated the classic game Pong entirely in custom hardware circuits on a programmable chip. Every pixel, paddle movement, score counter, and display signal is calculated instantly by dedicated physical logic gates, demonstrating how computer graphics can render in real time without needing a central processor or operating system.

intro

This project built a hardware-based VGA graphics engine and Pong video game in SystemVerilog, simulated with VCS, synthesized using Altera Quartus Prime, and deployed on a DE2-115 Development Board (Cyclone IV FPGA). Operating entirely at the register-transfer level (RTL), the system runs directly on clock division and hardware timers without soft-core processors or software instructions.

vga engine

We designed a custom VGA graphics engine to drive a standard $640 \times 480$ resolution at 60Hz. Because the FPGA operates on a fixed 50 MHz clock, we used clock division and counter logic in SystemVerilog to track the monitor’s scan beam position.

By tracking horizontal and vertical pixel counters, the hardware calculated when the scan beam was in the active display region and when it entered blanking intervals (front porch, sync pulse, back porch).

The 8-color bar test pattern output on a VGA monitor to confirm timing stability.

To verify timing logic on a physical monitor before adding game mechanics, we built a static test pattern generator. Dividing the screen into vertical color bars on the top half and solid black on the bottom half confirmed that color channels, active blanking, and sync pulses were aligned.

pong game mechanics

Once display timing was stable, we built the Pong game mechanics directly in hardware. The graphics engine dynamically checked whether current scan coordinates fell within paddle and ball bounding registers, rendering them on-the-fly against a dark blue background.

Designing game physics in pure hardware introduced a timing challenge: updating ball and paddle coordinates on every 50 MHz clock cycle caused the game to run too fast to be visible.

To fix this, we implemented a frame-rate synchronization circuit. Using a D-flip-flop division loop, we asserted a frame_finished trigger once per video frame (when the scan beam reached the bottom-right corner). This locked physics updates to a clean 60Hz. On each update, the datapath checked for overlapping bounding boxes between the ball, paddles, and screen edges, reversing velocity vectors ($dx, dy$) upon collision.

controls & debugging

For user inputs, players controlled the left and right paddles using toggle switches on the DE2-115 board.

FPGA Pong game in action on the monitor.

We routed score counters through a decimal decoder to display scores on 7-segment displays (HEX7 through HEX4). To simplify hardware debugging, we mapped FSM active state codes directly to HEX0, providing a real-time visual indicator of state transitions on the board.

Thank you to the 18-240 course staff for supplying the DE2-115 kits and lab resources.