18-447: introduction to computer architecture
teammates: frances adiwijiya, kody liang

tools: systemverilog, vcs, dc

💡 practical application

Every computer and smartphone relies on a Central Processing Unit (CPU) to execute instructions billions of times per second. This project built a 5-stage pipelined 32-bit RISC-V processor core from scratch. It uses assembly line pipelining (executing multiple instructions simultaneously at different stages), branch prediction (guessing where code will jump next to avoid delays), and fast cache memories to maximize computing speed.

intro

This project designed a 5-stage pipelined RISC-V processor core (RV32I ISA) in SystemVerilog, verified in simulation using VCS, and synthesized with Synopsys Design Compiler. Developed across four lab cycles, the microarchitecture evolved from a single-cycle design to a pipelined CPU featuring dynamic branch prediction and a set-associative cache subsystem.

pipeline architecture

The processor core uses a standard 5-stage instruction pipeline: Fetch (F), Decode (D), Execute (E), Memory (M), and Writeback (W):

  • Hazard Resolution: Data forwarding paths route execution results from Execute and Memory stages back to Decode, resolving RAW hazards without stalls (except single-cycle stalls for load-use dependencies).
  • Branch Prediction: A dynamic branch predictor in the Fetch stage speculatively fetches target instructions. Mispredictions detected in Decode or Execute flush speculative instructions to minimize branch penalties.

RISC-V 5-Stage Pipeline
5-stage pipelined datapath schematic with cache subsystem integration.

cache subsystem

To bridge the speed gap between core clock frequency and main memory latency, we integrated a set-associative cache in the Memory stage:

  • Configurable Associativity: Supports direct-mapped and multi-way set-associative layouts with parametric block offset, index, and way settings.
  • Miss Handler FSM: A cache miss halts the pipeline. The miss-handler FSM asserts memory bus signals to fetch the line from main memory, updates the target cache set, and resumes execution.
  • Eviction Policies: Implemented Least-Recently Used (LRU) replacement policy to minimize cache miss rates.

verification & synthesis

The core was verified against assembly and C benchmarks, comparing register dumps against a golden reference simulator (riscv-ref-sim).

Using Synopsys Design Compiler, we synthesized the CPU under timing constraints, analyzing critical path reports (timing_riscv_core.rpt) through register forwarding and cache lookup paths to meet target clock margins.