18-447: introduction to computer architecture
teammates: frances adiwijiya, kody liang

tools: systemverilog, vcs, dc

💡 practical application

Every computer and smartphone relies on a Central Processing Unit (CPU) to execute instructions billions of times per second. This project built a 5-stage pipelined 32-bit RISC-V processor core from scratch. It uses assembly line pipelining (executing multiple instructions simultaneously at different stages), branch prediction (guessing where code will jump next to avoid delays), and fast cache memories to maximize computing speed.

intro

A 5-stage pipelined RISC-V processor (supporting the RV32I ISA) designed and modeled in SystemVerilog, verified in simulation with VCS, and synthesized using Synopsys Design Compiler. Developed iteratively across four major lab cycles, the microarchitecture evolved from a simple single-cycle design to a pipelined CPU featuring dynamic branch prediction and a set-associative cache subsystem.

pipeline architecture

The processor core is structured around a standard 5-stage instruction pipeline: Fetch (F), Decode (D), Execute (E), Memory (M), and Writeback (W).

To maximize throughput and execution efficiency:

  • Hazard Resolution: We implemented comprehensive data forwarding paths from both the Execute and Memory stages back to the Decode stage. This resolves data hazards (RAW dependencies) without inserting stalls, except in the case of load-use dependencies where a single-cycle stall is inserted.
  • Branch Prediction: To minimize control hazard overhead, we integrated a branch prediction unit featuring a local branch predictor in the Fetch stage. Instructions are speculatively fetched based on the prediction. If the Decode or Execute stage detects a misprediction, the pipeline flushes the speculatively loaded instructions, minimizing branch penalties.

RISC-V 5-Stage Pipeline
5-stage pipelined datapath schematic with cache subsystem integration.

cache subsystem

To bridge the performance gap between the high-frequency core and slow external main memory, we designed and integrated a set-associative cache module in the Memory stage.

The cache subsystem features:

  • Configurable Associativity: Configurable set-associative layout supporting multiple index, block offset, and way parameters (e.g. Direct-Mapped vs. Multi-way set-associative cache structures).
  • Miss Stall Handler: Governed by an execution FSM, a cache miss halts the CPU pipeline. The miss-handler state machine asserts memory signals to fetch the missing block from external main memory, updates the cache set, and then resumes execution.
  • Eviction Policies: Supports replacement policies (such as Least-Recently Used (LRU)) to manage cache ways and minimize miss rates under dynamic memory access patterns.

verification & synthesis

The design was verified using a regression suite of assembly and C benchmarks. Register dumps at the end of simulation were automatically verified against the golden reference simulator (riscv-ref-sim).

For physical hardware mapping, we synthesized the CPU core under strict timing constraints using Design Compiler. We analyzed the timing report (timing_riscv_core.rpt) to trace critical paths through register forwarding and cache lookup paths, ensuring latch-free synthesis and meeting target timing margins.