18-622: digital ic design
teammates: kody liang

tools: virtuoso

💡 practical application

Static Random-Access Memory (SRAM) is the ultra-fast memory built directly inside computer processors (L1/L2 caches) to hold data for immediate calculation. Because SRAM cells operate at gigahertz speeds, they determine how quickly a chip can access data. This project designed a 4,096-cell SRAM memory chip at the individual transistor level on a 45-nanometer silicon process, optimizing layout geometry so memory reads and writes execute in under a nanosecond.

intro

This project designed a custom transistor-level 256 words × 16 bits SRAM (4,096 memory cells total) in Cadence Virtuoso using the GPDK045 (45nm) process technology. We optimized the architecture for speed, power, and layout density, achieving a clock frequency of 1.096 GHz in the worst-case TTLH process corner with a cell area efficiency of 58.26%.

architecture & floorplan

The memory array uses a pseudo-inverted-T floorplan to balance wordline and bitline delays:

  • Subarray Partitioning: The 4,096 cells split into two symmetric $64 \times 32$ cell subarrays.
  • Central Row Decoders: Row decoders sit in a central column between the subarrays. Driving wordlines (WL) from the center halves wire resistance to array edges, cutting propagation delay.
  • Column Multiplexing: Implemented a 4:1 column multiplexing factor. Each group of 4 columns shares a bitline reset block at the top and a cell I/O block at the bottom.
  • I/O Pitch Matching: Read/write column muxes, StrongArm sense amplifiers, and write drivers fit within the vertical pitch of 4 cell columns, eliminating routing congestion.

SRAM Pseudo-Inverted-T Floorplan
Pseudo-inverted-T floorplan diagram spanning two symmetric 64x32 cell arrays with central row decoders.

Cell I/O Layout
Layout of Cell I/O block, containing read/write multiplexers, StrongArm sense amplifier, and write driver.

circuit design & cell optimization

To ensure robust operation across PVT variations, every component was sized through static noise margin analysis:

  • 6T SRAM Cell: The core storage element is a standard 6-transistor (6T) cell. Transistors were sized to balance read stability and writeability, achieving a Read Static Noise Margin (Read SNM) of 498.8 mV and a maximum read current of 563.7 nA.
  • StrongArm Sense Amplifier: Utilized a StrongArm Sense-Amplifier Flip-Flop (SAFF) at the bottom of the read multiplexer. The latch-based structure resolves small bitline differentials quickly with zero static power dissipation.
  • Control Signal Generation: Bypassed replica bitline overhead by designing local inverter delay chains to generate clock-relative control pulses (WL_en, SE, WE, bl_rst_b).

6T SRAM Cell Schematic
Transistor-level schematic of the 6T SRAM cell (two cross-coupled inverters with access transistors).

6T SRAM Cell Layout
Physical symmetric layout of the 6T cell in Cadence Virtuoso (GPDK045 process).

verification & layout results

Interconnect resistance and capacitance for global wires (clock, Metal 6/2 wordlines, Metal 3 bitlines) were modeled with RC $\pi$-networks and verified using post-layout parasitic extraction (Assura AV_extract):

  • Performance: Achieved a 912 ps cycle time (1.096 GHz) under the worst-case TTLH process corner.
  • Power: Consumes 2.053 mW of total power at a 50/50 read/write mix (1.662 mW dynamic, 391 $\mu$W static).
  • Area: The complete layout fits in a bounding box of $115.7 \mu m \times 44.865 \mu m$ ($5,191 \mu m^2$), yielding an overall cell area efficiency of 58.26%.

SRAM Final Bounding Box Silicon Layout
Complete silicon layout bounding box (115.7μm x 44.865μm) showing the pseudo-inverted-T symmetry.

Worst-Case Simulation Waveforms
Analog simulation waveforms exercising the critical path read operation under worst-case timing.